View 25LC320A-HSN_1133111.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2009 microchip technology inc. preliminary ds22131b-page 1 25lc080c 25lc320a 25lc080d 25lc640a 25lc160c 25lc128 25lc160d 25lc256 features: ? max. clock 5 mhz ? low-power cmos technology: - max. write current: 5 ma at 5.5v, 5 mhz - read current: 5 ma at 5.5v, 5 mhz - standby current: 10 a at 5.5v ? 1024 x 8 through 32768 x 8-bit organization ? byte and page-level write operations ? self-timed erase and write cycles (6 ms max.) ? block write protection: - protect none, 1/4, 1/2 or all of array ? built-in write protection: - power-on/off data protection circuitry - write enable latch - write-protect pin ? sequential read ? high reliability: - endurance: >100k erase/write cycles - data retention: > 200 years - esd protection: > 4000v ? temperature range supported: ? package is pb-free and halogen free pin function table description: microchip technology inc. 25lcxxx* devices are mid- density 8 through 256 kbit serial electrically erasable proms (eeprom). the devices are organized in blocks of x8-bit memory and support the serial periph- eral interface (spi) compatible serial bus architecture. byte-level and page-level functions are supported. the bus signals required are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input. communication to the device can be paused via the hold pin (hold ). while the device is paused, transi- tions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. the 25lcxxx is available in a standard 8-lead soic package. the package is pb-free. package types (not to scale) - extended (h): -40c to +150c name function cs chip select input so serial data output wp write-protect v ss ground si serial data input sck serial clock input hold hold input v cc supply voltage cs so wp v ss 1 2 3 4 8 7 6 5 v cc hold sck si soic (sn) 8k-256k spi serial eeprom high temp family data sheet *25lcxxx is used in this document as a generic part number for the 25 series devices.
25lcxxx ds22131b-page 2 preliminary ? 2009 microchip technology inc. device selection table part number density (bits) organization v cc range max speed (mhz) page size (bytes) temp. range package 25lc080c 8k 1,024 x 8 2.5v - 5.5v 5 16 h sn 25lc080d 8k 1,024 x 8 2.5v - 5.5v 5 32 h sn 25lc160c 16k 2,048 x 8 2.5v - 5.5v 5 16 h sn 25lc160d 16k 2,048 x 8 2.5v - 5.5v 5 32 h sn 25lc320a 32k 4,096 x 8 2.5v - 5.5v 5 32 h sn 25lc640a 64k 8,192 x 8 2.5v - 5.5v 5 32 h sn 25lc128 128k 16,384 x 8 2.5v - 5.5v 5 64 h sn 25lc256 256k 32,768 x 8 2.5v - 5.5v 5 64 h sn
? 2009 microchip technology inc. preliminary ds22131b-page 3 25lcxxx 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ..........................................................................................................-0.6v to v cc +1.0v storage temperature ............................................................................................................ ..................... -65c to 155c ambient temperature under bias................................................................................................. .......... -40c to 150c (1) esd protection on all pins..................................................................................................... ..................................... 4 kv table 1-1: dc characteristics note 1: aec-q100 reliability testing for devices intended to operate at 150c is 1,000 hours. any design in which the total operating time between 125c and 150c will be greater than 1,000 hours is not warranted with- out prior written approval from microchip technology inc. ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for an extended period of time may affect device reliability. dc characteristics extended (h): t a = -40c to +150c v cc = 2.5v to 5.5v param. no. sym. characteristic min. max. units test conditions d001 v ih 1 high-level input voltage .7 v cc v cc +1 v d002 v il 1 low-level input voltage -0.3 0.3v cc vv cc 2.7v d003 v il 2 -0.3 0.2v cc vv cc < 2.7v d004 v ol 1 low-level output voltage ?0.4vi ol = 2.1 ma d005 v ol 2 ?0.2vi ol = 1.0 ma d006 v oh high-level output voltage v cc -0.5 ? v i oh = -400 a d007 i li input leakage current ? 2 acs = v cc , v in = v ss or v cc d008 i lo output leakage current ?2 acs = v cc , v out = v ss or v cc d009 c int internal capacitance (all inputs and outputs) ?7pft a = 25c, clk = 1.0 mhz, v cc = 5.0v (note) d010 i cc read operating current ? ? 5 2.5 ma ma v cc = 5.5v; f clk = 5.0 mhz; so = open v cc = 2.5v; f clk = 3.0 mhz; so = open d011 i cc write ? ? 5 3 ma ma v cc = 5.5v v cc = 2.5v d012 i ccs standby current ? 10 acs = v cc = 5.5v, inputs tied to v cc or v ss , 150c note: this parameter is periodically sampled and not 100% tested.
25lcxxx ds22131b-page 4 preliminary ? 2009 microchip technology inc. table 1-2: ac characteristics ac characteristics extended (h): t a = -40c to +150c v cc = 2.5v to 5.5v param. no. sym. characteristic min. max. units test conditions 1f clk clock frequency ? ? 5 3 mhz mhz 4.5v vcc 5.5v 2.5v vcc < 4.5v 2t css cs setup time 100 150 ? ? ns ns 4.5v vcc 5.5v 2.5v vcc < 4.5v 3t csh cs hold time 200 250 ? ? ns ns 4.5v vcc 5.5v 2.5v vcc < 4.5v 4t csd cs disable time 50 ? ns ? 5 tsu data setup time 20 30 ? ? ns ns 4.5v vcc 5.5v 2.5v vcc < 4.5v 6t hd data hold time 40 50 ? ? ns ns 4.5v vcc 5.5v 2.5v vcc < 4.5v 7t r clk rise time ? 2 s (note 1) 8t f clk fall time ? 2 s (note 1) 9t hi clock high time 100 150 ? ? ns ns 4.5v vcc 5.5v 2.5v vcc < 4.5v 10 t lo clock low time 100 150 ? ? ns ns 4.5v vcc 5.5v 2.5v vcc < 4.5v 11 t cld clock delay time 50 ? ns ? 12 t cle clock enable time 50 ? ns ? 13 t v output valid from clock low ? ? 100 160 ns ns 4.5v vcc 5.5v 2.5v vcc < 4.5v 14 t ho output hold time 0 ? ns (note 1) 15 t dis output disable time ? ? 80 160 ns ns 4.5v vcc 5.5v (note 1) 2.5v vcc 4.5v (note 1) 16 t hs hold setup time 40 80 ? ? ns ns 4.5v vcc 5.5v 2.5v vcc < 4.5v 17 t hh hold hold time 40 80 ? ? ns ns 4.5v vcc 5.5v 2.5v vcc < 4.5v 18 t hz hold low to output high-z 60 160 ? ? ns ns 4.5v vcc 5.5v (note 1) 2.5v vcc < 4.5v (note 1) 19 t hv hold high to output valid 60 160 ? ? ns ns 4.5v vcc 5.5v 2.5v vcc < 4.5v 20 t wc internal write cycle time ? 6 ms (note 2) 21 ? endurance 100k ? e/w cycles (note 3) note 1: this parameter is periodically sampled and not 100% tested. 2: t wc begins on the rising edge of cs after a valid write sequence and ends when the internal write cycle is complete. 3: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be obtained from our web site: www.microchip.com.
? 2009 microchip technology inc. preliminary ds22131b-page 5 25lcxxx table 1-3: ac test conditions ac waveform: v lo = 0.2v ? v hi = v cc ? 0.2v (note 1) v hi = 4.0v (note 2) c l = 50 pf ? timing measurement reference level input 0.5 v cc output 0.5 v cc note 1: for v cc 4.0v 2: for v cc > 4.0v
25lcxxx ds22131b-page 6 preliminary ? 2009 microchip technology inc. figure 1-1: hold timing figure 1-2: serial input timing figure 1-3: serial output timing cs sck so si hold 17 16 16 17 19 18 don?t care 5 high-impedance n + 2 n + 1 n n - 1 n n + 2 n + 1 n n n - 1 cs sck si so 6 5 8 7 11 3 lsb in msb in high-impedance 12 mode 1 , 1 mode 0 , 0 2 4 cs sck so 10 9 13 msb out isb out 3 15 don?t care si mode 1 , 1 mode 0 , 0 14
? 2009 microchip technology inc. preliminary ds22131b-page 7 25lcxxx 2.0 pin descriptions the descriptions of the pins are listed in table 2-1. table 2-1: pin function table 2.1 chip select (cs ) a low level on this pin selects the device. a high level deselects the device and forces it into standby mode. however, a programming cycle which is already initiated or in progress will be completed, regardless of the cs input signal. if cs is brought high during a program cycle, the device will go into standby mode as soon as the programming cycle is complete. when the device is deselected, so goes to the high-impedance state, allowing multiple parts to share the same spi bus. a low-to-high transition on cs after a valid write sequence initiates an internal write cycle. after power- up, a low level on cs is required prior to any sequence being initiated. 2.2 serial output (so) the so pin is used to transfer data out of the 25lcxxx. during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 2.3 write-protect (wp ) this pin is used in conjunction with the wpen bit in the status register to prohibit writes to the nonvolatile bits in the status register. when wp is low and wpen is high, writing to the nonvolatile bits in the sta- tus register is disabled. all other operations function normally. when wp is high, all functions, including writes to the nonvolatile bits in the status register operate normally. if the wpen bit is set, wp low during a status register write sequence will disable writing to the status register. if an internal write cycle has already begun, wp going low will have no effect on the write. the wp pin function is blocked when the wpen bit in the status register is low. this allows the user to install the 25lcxxx in a system with wp pin grounded and still be able to write to the status register. the wp pin functions will be enabled when the wpen bit is set high. 2.4 serial input (si) the si pin is used to transfer data into the device. it receives instructions, addresses and data. data is latched on the rising edge of the serial clock. 2.5 serial clock (sck) the sck is used to synchronize the communication between a master and the 25lcxxx. instructions, addresses or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. 2.6 hold (hold ) the hold pin is used to suspend transmission to the 25lcxxx while in the middle of a serial sequence without having to retransmit the entire sequence again. it must be held high any time this function is not being used. once the device is selected and a serial sequence is underway, the hold pin may be pulled low to pause further serial communication without resetting the serial sequence. the hold pin must be brought low while sck is low, otherwise the hold function will not be invoked until the next sck high-to- low transition. the 25lcxxx must remain selected during this sequence. the si, sck and so pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. to resume serial communication, hold must be brought high while the sck pin is low, otherwise serial communication will not resume. lowering the hold line at any time will tri-state the so line. name pin number function cs 1 chip select input so 2 serial data output wp 3 write-protect pin v ss 4 ground si 5 serial data input sck 6 serial clock input hold 7 hold input v cc 8 supply voltage
25lcxxx ds22131b-page 8 preliminary ? 2009 microchip technology inc. 3.0 functional description 3.1 principles of operation the 25lcxxx are mid-density serial eeproms designed to interface directly with the serial peripheral interface (spi) port of many of today?s popular micro- controller families, including microchip?s pic ? micro- controllers. it may also interface with microcontrollers that do not have a built-in spi port by using discrete i/ o lines programmed properly in firmware to match the spi protocol. the 25lcxxx contains an 8-bit instruction register. the device is accessed via the si pin, with data being clocked in on the rising edge of sck. the cs pin must be low and the hold pin must be high for the entire operation. table 3-1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses, and data are transferred msb first, lsb last. data (si) is sampled on the first rising edge of sck after cs goes low. if the clock line is shared with other peripheral devices on the spi bus, the user can assert the hold input and place the 25lcxxx in ?hold? mode. after releasing the hold pin, operation will resume from the point when the hold was asserted. block diagram si so sck cs hold wp status register i/o control memory control logic x dec hv generator eeprom array page latches y decoder sense amp. r/w control logic v cc v ss table 3-1: instruction set instruction name instruction format description read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address wrdi 0000 0100 reset the write enable latch (disable write operations) wren 0000 0110 set the write enable latch (enable write operations) rdsr 0000 0101 read status register wrsr 0000 0001 write status register
? 2009 microchip technology inc. preliminary ds22131b-page 9 25lcxxx 3.2 read sequence the device is selected by pulling cs low. the 8-bit read instruction is transmitted to the 25lcxxx fol- lowed by the 16-bit address. after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. the data stored in the memory at the next address can be read sequentially by continuing to pro- vide clock pulses. the internal address pointer is auto- matically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. the read operation is terminated by raising the cs pin (figure 3-1). 3.3 write sequence prior to any attempt to write data to the 25lcxxx, the write enable latch must be set by issuing the wren instruction (figure 3-4). this is done by setting cs low and then clocking out the proper instruction into the 25lcxxx. after all eight bits of the instruction are transmitted, the cs must be brought high to set the write enable latch. if the write operation is initiated immediately after the wren instruction without cs being brought high, the data will not be written to the array because the write enable latch will not have been properly set. once the write enable latch is set, the user may proceed by setting the cs low, issuing a write instruc- tion, followed by the 16-bit address, and then the data to be written. depending upon the density, a page of data that ranges from 16 bytes to 64 bytes can be sent to the device before a write cycle is necessary. the only restriction is that all of the bytes must reside in the same page. for the data to be actually written to the array, the cs must be brought high after the least significant bit (d0) of the n th data byte has been clocked in. if cs is brought high at any other time, the write operation will not be completed. refer to figure 3-2 and figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. while the write is in progress, the status register may be read to check the status of the wpen, wip, wel, bp1 and bp0 bits (figure 3-6). a read attempt of a memory array location will not be possible during a write cycle. when the write cycle is completed, the write enable latch is reset. figure 3-1: read sequence note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or ?page size?) and, end at addresses that are integer multiples of page size ? 1. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. so si sck cs 0 234567891011 21222324252627282930 31 1 01 0 0 0 0 01 15 14 13 12 210 76543210 instruction 16-bit address data out high-impedance
25lcxxx ds22131b-page 10 preliminary ? 2009 microchip technology inc. figure 3-2: byte write sequence figure 3-3: page write sequence so si cs 9 1011 21222324252627282930 31 00 0 0 0 0 01 15 14 13 12 210 76543210 instruction 16-bit address data byte high-impedance sck 0 234567 18 twc si cs 9 1011 21222324252627282930 31 00 0 0 0 0 01 15 14 13 12 210 76543210 instruction 16-bit address data byte 1 sck 0 234567 1 8 si cs 41 42 43 46 47 76543210 data byte n (16/32/64 max) sck 32 34 35 36 37 38 39 33 40 76543210 data byte 3 76543210 data byte 2 44 45
? 2009 microchip technology inc. preliminary ds22131b-page 11 25lcxxx 3.4 write enable ( wren ) and write disable ( wrdi ) the 25lcxxx contains a write enable latch. see table 5-1 for the write-protect functionality matrix. this latch must be set before any write operation will be com- pleted internally. the wren instruction will set the latch, and the wrdi will reset the latch. the following is a list of conditions under which the write enable latch will be reset: ? power-up ? wrdi instruction successfully executed ? wrsr instruction successfully executed ? write instruction successfully executed figure 3-4: write enable sequence ( wren ) figure 3-5: write disable sequence ( wrdi ) sck 0 234567 1 si high-impedance so cs 01 0000 0 1 sck 0 234567 1 si high-impedance so cs 01 0000 0 1 0
25lcxxx ds22131b-page 12 preliminary ? 2009 microchip technology inc. 3.5 read status register instruction ( rdsr ) the read status register instruction ( rdsr ) provides access to the status register. the status register may be read at any time, even during a write cycle. the status register is formatted as follows: table 3-2: status register the write-in-process (wip) bit indicates whether the 25lcxxx is busy with a write operation. when set to a ? 1 ?, a write is in progress, when set to a ? 0 ?, no write is in progress. this bit is read-only. the write enable latch (wel) bit indicates the status of the write enable latch and is read-only. when set to a ? 1 ?, the latch allows writes to the array, when set to a ? 0 ?, the latch prohibits writes to the array. the state of this bit can always be updated via the wren or wrdi commands regardless of the state of write protection on the status register. these commands are shown in figure 3-4 and figure 3-5. the block protection (bp0 and bp1) bits indicate which blocks are currently write-protected. these bits are set by the user issuing the wrsr instruction. these bits are nonvolatile, and are shown in table 3-3. see figure 3-6 for the rdsr timing sequence. figure 3-6: read status register timing sequence ( rdsr ) 7 654 3 2 1 0 w/r ???w/rw/r r r wpen x x x bp1 bp0 wel wip w/r = writable/readable. r = read-only. so si cs 91011 12131415 11 0 0 0 0 00 7654 2 10 instruction data from status register high-impedance sck 0 234567 1 8 3
? 2009 microchip technology inc. preliminary ds22131b-page 13 25lcxxx 3.6 write status register instruction ( wrsr ) the write status register instruction ( wrsr ) allows the user to write to the nonvolatile bits in the status register as shown in table 3-2. the user is able to select one of four levels of protection for the array by writing to the appropriate bits in the status register. the array is divided up into four segments. the user has the ability to write-protect none, one, two or all four of the segments of the array. the partitioning is controlled as shown in table 3-3. the write-protect enable (wpen) bit is a nonvolatile bit that is available as an enable bit for the wp pin. the write-protect (wp ) pin and the write-protect enable (wpen) bit in the status register control the programmable hardware write-protect feature. hard- ware write protection is enabled when wp pin is low and the wpen bit is high. hardware write protection is disabled when either the wp pin is high or the wpen bit is low. when the chip is hardware write-protected, only writes to nonvolatile bits in the status register are disabled. see table 5-1 for a matrix of functionality on the wpen bit. see figure 3-7 for the wrsr timing sequence. table 3-3: array protection table 3-4: array protected address locations figure 3-7: write status register timing sequence ( wrsr ) bp1 bp0 array addresses write-protected array addresses unprotected 00 none all 01 upper 1/4 lower 3/4 10 upper 1/2 lower 1/2 11 all none density upper 1/4 upper 1/2 all 8k 300h - 3ffh 200h - 3ffh 000h - 3ffh 16k 600h - 7ffh 400h - 7ffh 000h - 7ffh 32k c00h - fffh 800h - fffh 000h - fffh 64k 1800h - 1fffh 1000h - 1fffh 0000h - 1fffh 128k 3000h - 3fffh 2000h - 3fffh 0000h - 3fffh 256k 6000h - 7fffh 4000h - 7fffh 0000h - 7fffh so si cs 91011 12131415 0 1 0 0 0 0 00 7654 210 instruction data to status register high-impedance sck 0 234567 1 8 3 note: an internal write cycle (t wc ) is initiated on the rising edge of cs after a valid write status register sequence.
25lcxxx ds22131b-page 14 preliminary ? 2009 microchip technology inc. 4.0 data protection the following protection has been implemented to prevent inadvertent writes to the array: ? the write enable latch is reset on power-up ? a write enable instruction must be issued to set the write enable latch ? after a byte write, page write or status register write, the write enable latch is reset ?cs must be set high after the proper number of clock cycles to start an internal write cycle ? access to the array during an internal write cycle is ignored and programming is continued 5.0 power-on state the 25lcxxx powers on in the following state: ? the device is in low-power standby mode (cs = 1 ) ? the write enable latch is reset ? so is in high-impedance state ? a high-to-low-level transition on cs is required to enter active state table 5-1: write-protec t functionality matrix wel (sr bit 1) wpen (sr bit 7) wp (pin 3) protected blocks unprotected blocks status register 0xx protected protected protected 10x protected writable writable 110 (low) protected writable protected 111 (high) protected writable writable x = don?t care
? 2009 microchip technology inc. preliminary ds22131b-page 15 25lcxxx 6.0 packaging information 6.1 package marking information note : custom marking available. 8-lead soic xxxxyyww xxxxxxxt nnn example: sn 0728 25lc32ah 1l7 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 8-lead soic package marking (pb-free) device line 1 marking 25lc080c 25lc80ct 25lc080d 25lc80dt 25lc160c 25lc16ct 25lc160d 25lc16dt 25lc320a 25lc32at 25lc640a 25l640at 25lc128 25lc128t 25lc256 25lc256t note 1: t = temperature grade (h).
25lcxxx ds22131b-page 16 preliminary ? 2009 microchip technology inc.

!"#$% & !" #$ %! &'(!%&! %( % ")%% % " *$%+% % , & "-"%!" &"$
%! "$
%! % # ".&&
" & "%
-/. 0+1 0 & % #%! ))%!%% -21 $ & '! !)%!%% '$$&%
!
& 2% & %! %
3 ") '
%
3
$%% "% %%
144)))&
&4
3 5% 66-- & 6&% 7 78 9 7!&( $ 7 : % 0+ 8 ; % < < . " "3 3 . < < %"$$ * < . 8 ="% - >0+ " "3 ="% - ,0+ 8 6 % 0+ +&$ ?
%@ . < . 2%6 % 6 < 2%
% 6 -2 2% a < :a 6 "3 < . 6 "="% ( , < . "$%
.a < .a "$% 0%%& .a < .a d n e e e1 note 1 12 3 b a a1 a2 l l1 c h h
) + .0
? 2009 microchip technology inc. preliminary ds22131b-page 17 25lcxxx

!"#$% & 2% & %! %
3 ") '
%
3
$%% "% %%
144)))&
&4
3
25lcxxx ds22131b-page 18 preliminary ? 2009 microchip technology inc. revision history revision a (01/2009) original release. revision b (04/2009) revised part number from 25xx to 25lcxxx; added note 1 to electrical characteristics.
? 2009 microchip technology inc. preliminary ds22131b-page 19 25lcxxx the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following informa- tion: ? product support ? data sheets and errata, appli- cation notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of micro- chip sales offices, distributors and factory repre- sentatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notifi- cation and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representa- tive or field application engineer (fae) for support. local sales offices are also available to help custom- ers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
25lcxxx ds22131b-page 20 preliminary ? 2009 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds22131b 25lcxxx 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2009 microchip technology inc. preliminary ds22131b-page 21 25lcxxx product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx package tape & reel device device: 25lc080c = 25lc080d = 25lc160c = 25lc160d = 25lc320a = 25lc640a = 25lc128 = 25lc256 = 8k-bit, 2.5v, 16 byte page, spi serial eeprom 8k-bit, 2.5v, 32 byte page, spi serial eeprom 16k-bit, 2.5v, 16 byte page, spi serial eeprom 16k-bit, 2.5v, 32 byte page, spi serial eeprom 32k-bit, 2.5v, 32 byte page, spi serial eeprom 64k-bit, 2.5v, 32 byte page, spi serial eeprom 128k-bit, 2.5v, 64 byte page, spi serial eeprom 256k-bit, 2.5v, 64 byte page, spi serial eeprom tape & reel: blank = t= standard packaging ta p e & r e e l temperature range: h= -40 c to+150 c package: sn = plastic soic (3.90 mm body), 8-lead examples: a) 25lc080ct-h/sn = 8k-bit, 16-byte page, 2.5v serial eeprom, extended temp., tape & reel, soic package b) 25lc080d-h/sn = 8k-bit, 32-byte page, 2.5v serial eeprom, extended temp., soic pack- age c) 25lc160ct-h/sn = 16k-bit, 16-byte page, 2.5v serial eeprom, extended temp., tape & reel, soic package d) 25lc160d-h/sn = 16k-bit, 32-byte page, 2.5v serial eeprom, extended temp., soic pack- age e) 25lc320at-h/sn = 32k-bit, 32-byte page, 2.5v serial eeprom, extended temp., tape & reel, soic package f) 25lc640a-h/sn = 64k-bit, 32-byte page, 2.5v serial eeprom, extended temp., soic pack- age g) 25lc128t-h/sn = 128k-bit, 64-byte page, 2.5v serial eeprom, extended temp., tape & reel, soic package h) 25lc256-h/sn = 256k-bit, 64-byte page, 2.5v serial eeprom, extended temp., soic pack- age ? x tem p range
25lcxxx ds22131b-page 22 preliminary ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. preliminary ds22131b-page 23 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic, smartshunt and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. filterlab, hampshire, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, nanowatt xlp, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, tsha rc, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
ds22131b-page 24 preliminary ? 2009 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4080 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-6578-300 fax: 886-3-6578-370 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 03/26/09

▲Up To Search▲

Price & Availability of 25LC320A-HSN

	To Download 25LC320A-HSN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .